Quantum paper

Quantum error correction (logical qubits below threshold)

Crossed theoretical threshold for scalable quantum computing; demonstrated exponential error suppression on real hardware for the first time, moving from physics milestone to engineering milestone.

What to watch next

Fault-tolerant quantum computers with 10+ logical qubits demonstrating practical speedup (2025-2026); Riverlane's MegaQuOp (1 million error-free operations) target by 2026.

Key sub-ideas & techniques

• Surface code below threshold — Google Willow (Dec 2024, 105 qubits) was the first hardware to show that increasing the surface-code distance suppresses logical error exponentially — the long-promised threshold theorem realized in silicon. [source]
• Logical qubits with virtualization — Quantinuum + Microsoft demonstrated 4 logical qubits with 800x lower error than physical qubits using ion-trap hardware and run-time mid-circuit measurement, validating a different path to QEC. [source]
• Bivariate bicycle / qLDPC codes — IBM's bivariate bicycle codes (Nature 2024) need ~10x fewer physical qubits per logical qubit than the surface code, potentially shrinking the path to fault tolerance from millions of qubits to ~hundreds of thousands. [source]
• Cat qubits & bosonic codes — Encoding a logical qubit in the photons of a microwave cavity (Alice & Bob, AWS) intrinsically suppresses bit-flip errors, reducing the QEC overhead and offering an alternative to surface codes. [source]
• Real-time decoding hardware — Riverlane's DD1 and Google's custom decoders move syndrome decoding into dedicated FPGA / ASIC, the missing piece for sustained logical operation — the 'CPU' for the quantum 'GPU'. [source]
• Logical-qubit advantage on real applications (neutral atoms) — First demonstration that logical qubits outperform physical qubits on an end-to-end real-world task (differential equations) on a neutral-atom processor at 99.4% gate fidelity across 1,000 equations. [source]
• Barbell codes (qLDPC) — A new family of quantum low-density parity-check error-correcting codes designed for IQM's superconducting Constellation processor, reducing logical error rates and physical-qubit overhead versus the surface code. [source]
• Dual-rail superconducting qubits for fault tolerance — Erasure-biased dual-rail encoding (photon-loss/leakage detected as erasures) in superconducting circuits, now pursued by D-Wave via its Quantum Circuits Inc. acquisition as a lower-overhead route to logical qubits, distinct from transmon surface-code approaches. [source]
• Q-PLANET — Pasqal-coordinated EU Chips JU pilot manufacturing line for neutral-atom quantum chip components
• Crypto-Agility Readiness Score — Benchmark of 43 repos vs NIST PQC standards; legacy libs avg 24.9/100 [source]
• Mitten codes (qLDPC) — High-rate (~20%) qLDPC code family with fault-tolerant surgery gadgets and a fast decoder (Caltech, arXiv:2607.28795, Jul 30 2026). [source]
• Verifiable provable advantage — Advantage demonstrations with a mathematical proof (not conjecture) and efficient classical verification of the output. [source]
• Sandia/Quantinuum/NVIDIA launch QUOPS cross-platform quantum benchmark — The QUOPS framework benchmarks full-system quantum performance: Quantinuum Helios-1 scored Q=1,504 physical and Q=40 on an 8-logical-qubit Steane [[7,1,3]] configuration vs Google Willow's Q=216 and IBM ibm_boston's Q=204; utility-scale problems need Q≈2.5–3.4×10^8. [source]
• Scalable logical qubit definition — Proposed grading standard for logical-qubit claims. [source]
• Quantinuum Helios 99.9995% color-code logical fidelity — On Oct 19 Quantinuum reported a logical error rate of 5 per million QEC rounds (distance 7) on Helios, 10x below its own September Helix result. Each code-distance step cut logical errors about 12x (5.5e-4 at d3, 3.8e-5 at d5, 5e-6 at d7); the color code uses up to 37 physical qubits per logical qubit versus 10 for Helix. d7 figure rests on 3 failures in 29,000 runs; preprint not yet peer reviewed. [source]
• Nvidia 104-qubit FTQC noisy simulation on JUPITER — Announced at GTC Berlin (reported Oct 19-21): largest full-state simulation of a fault-tolerant quantum processor with realistic noise (104 qubits, 8,192 GH200 GPUs on JUPITER), modeling magic state cultivation that Nvidia says needs 90% fewer qubits (vendor claim). Classical simulation only, no quantum hardware; prior Julich run was 50 noiseless qubits (Nov 2025). [source]

Current frontier

• Google Willow (December 2024): 105-qubit processor achieved surface code error suppression below threshold with distance-7 code at 0.143% per-cycle logical error rate; first demonstration of exponential error suppression with increasing code size [source]
• Microsoft-Quantinuum (April 2024): Demonstrated 4 logical qubits with error rates 800x lower than physical qubits; 14,000+ experiments without error using trapped-ion hardware with qubit virtualization [source]
• IBM (2024): Surface code distance-5 implementation with logical error suppression, decoding in 135 microseconds on laptop; bivariate bicycle codes show 27x speedup at 0.3% circuit-level error rates [source]
• Quantinuum Helios (2025): 3rd generation ion-trap quantum computer with 99.921% 2-qubit gate fidelity; first complete quantum chemistry simulation using QEC on real hardware [source]
• Riverlane DD1 QEC Chip (2024): Dedicated quantum error correction ASIC/FPGA achieving logical error rate of 1 in a trillion; published in Nature Electronics with end-to-end hardware validation [source]
• NVIDIA Ising open AI models accelerate QEC decoding/calibration with sub-microsecond latency, 2.5x speedup and 3x accuracy gains over classical baselines. [source]
• US federal industrial policy is now explicitly steering quantum hardware build-out at the foundry level — a structural shift from research grants to manufacturing capacity formation, with $2B in CHIPS funding distributed across nine vendors on May 21, 2026. [source]
• Flatiron Institute CCQ + Boston University demonstrated (Science, May 21 2026) that a tensor-network algorithm, running on a laptop, can classically simulate the same 100-qubit highly-entangled dynamics problem D-Wave used to claim 'beyond-classical' computation with its 5,000-qubit Advantage2 annealer in March 2025 — resetting where the quantum-advantage line sits. [source]
• IBM disclosed $10B five-year quantum push (May 28, 2026) spanning R&D, manufacturing, partnerships and the Anderon foundry with DoC ($1B CHIPS proposed); targets Starling fault-tolerant machine by 2029. [source]
• On a trapped-ion QCCD processor, two optimized QEC code constructions (12-qubit Knill-inspired and 16-qubit tesseract colour code) combined with scalable error detection achieve logical error rates 11x to 800x lower than physical-circuit baselines; now published in Nature (vol 654, pp 349-355, 2026). [source]
• Quantinuum 98-qubit Helios (Nature, June 17): 99.9975% 1q / 99.921% 2q fidelity, 99.967% SPAM; Sandia certified beyond-classical operation. [source]
• HPE's hybrid quantum-HPC platform (HPE Discover, June 15-18) integrates Quantinuum + IQM QPUs with Cray supercomputing for enterprise quantum-classical workflows. [source]
• IQM directional tile codes: up to 1,000x lower logical error rate vs surface code at ~30 physical qubits/logical, native iSWAP gates on existing hardware. [source]
• University of Sydney + IBM (156-qubit Heron r2): mid-circuit measurement idling noise is a dominant QEC error source; addressing it lifts logical qubit survival from <90% to >96% per cycle (Nature Communications, July 6, 2026). [source]
• At HPE Discover (June 15-18), HPE unveiled a hybrid classical-quantum platform integrating multiple qubit modalities with Cray supercomputing; Quantinuum announced a quantum-HPC collaboration and IQM (already tracked) contributed superconducting QPU tech live at Oak Ridge — pushing quantum-classical hybrid orchestration toward enterprise deployment. [source]
• IBM Nighthawk r2 (120 qubits): tunable-coupler reset ~200µs→25ns, ~25x throughput, 11x lower init error; Qiskit v2.5. [source]
• Quantinuum (Nature, Jul 15 2026): first universal gate set from anyon braiding+fusion on the 54-qubit H2 trapped-ion system (non-Abelian S3 order). [source]
• 12 logical qubits (Steane code) running QFT on Quantinuum Helios; 98 physical qubits for the approximate variant. [source]
• A Swap-Wait-Swap CZ gate between dual-rail cavity qubits reached ~99.9% two-qubit fidelity at ~500ns with ~0.5% erasure rate and post-selected residual Pauli errors below 0.1% - a hardware step toward efficient error-corrected gate-model quantum computing. [source]
• Helix architecture on Helios: logical memory 9.3e-5/round, logical Clifford 2.8e-4 (4.28x below physical), 3-logical-qubit GHZ >99.925%, no post-selection. [source]
• IBM Nighthawk r2 (120q): 100K+ circuits/sec, accurate observables at 7,500+ two-qubit gates — 2026 roadmap milestone early. [source]
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• Jülich benchmark: Quantinuum Helios-1 stands out on QEC-style mid-circuit measurement — Preprint arXiv 2610.05928 (Jülich Supercomputing Centre; covered Oct 8, 2026) compared 10 Quantinuum/IBM/IQM processors: IBM measurement-based circuits showed ~10x higher effective error, while Helios-1 stayed above random up to 81 (surface) and 91 (color) data qubits; the 30-qubit chain comparison was inconclusive. Not a QEC demonstration; not peer reviewed. [source]

Key people

• Hartmut Neven Founder and Lead, Google Quantum AI; VP Engineering · Google [source]
• John Preskill Director, Institute for Quantum Information & Matter; Professor of Theoretical Physics · California Institute of Technology (Caltech) [source]
• Ilyas Khan Founder & Chief Product Officer; Vice-Chairman of Board · Quantinuum [source]
• Barbara Terhal Professor of Quantum Information; Research Scientist · QuTech & DIAM, Delft University of Technology (TU Delft) [source]
• Steve Brierley Founder and CEO · Riverlane [source]
• David Hayes Senior Quantum Physicist; Logical Qubit Research Lead · Quantinuum [source]
• John Martinis Co-founder & CTO · Qolab [source]

Startups & labs to watch

• PsiQuantum PsiQuantum (photonic quantum computing) · STARTUP · Significant DARPA backing; private funding round details proprietary — DARPA US2QC program finalist (Feb 2025) pursuing surface codes on photonic qubits; broke ground on largest US quantum computing project at Illinois facility; targeting utility-scale quantum computer by 2033 [source]
• Atom Computing Atom Computing (neutral-atom quantum computing) · STARTUP · Series B/C rounds; corporate backing from aerospace partners — Scaling neutral-atom systems for QEC; announced 1,000+ qubit demonstration targets; competing with Quantinuum (trapped ions) and Google (superconducting) on QEC roadmaps [source]
• Alice & Bob Alice & Bob (bosonic quantum computing) · STARTUP · $50M+ Series B; European backing — Developing cat-qubits and bosonic codes as alternative to surface codes; co-hosted Fault Tolerance Summit (Les Houches 2024); raised $50M+ Series B [source]
• Anderon IBM (spinout) + U.S. Department of Commerce · STARTUP · $2B total ($1B IBM cash + IP/assets; $1B proposed CHIPS Act incentive) — First purpose-built US quantum foundry — provides shared, scaled 300mm fabrication for IBM, Quantinuum, Diraq, Microsoft and other modalities, addressing the wafer-supply bottleneck for fault-tolerant systems. [source]
• HRL Laboratories HRL Laboratories (Boeing/GM joint venture) · LAB · M&A by IBM (terms undisclosed) — Silicon-spin-qubit + quantum-sensing expertise folded into IBM's fault-tolerance roadmap (Starling 2029) [source]
• Quantum Circuits Inc (QCI) Quantum Circuits Inc (acquired by D-Wave, Jan 2026) · STARTUP · Acquired by D-Wave for $550M (Jan 2026) — Originated the dual-rail erasure-qubit modality now central to D-Wave's gate-model roadmap - the dependency entity behind this week's Nature result [source]
• Infleqtion (x Cisco quantum networking) Infleqtion / Cisco Quantum Labs · STARTUP · Public company (NYSE: INFQ via SPAC, 2026) — First neutral-atom vendor pairing with a networking incumbent on a full distributed-quantum stack; also strong in atomic clocks/sensing. [source]
• IonQ QCE26 research program IonQ · LAB — Four Best Paper Awards in one year signals maturing hybrid quantum-classical applications across chemistry, logistics and AI fine-tuning [source]
• Pasqal FTQC national programme Pasqal FTQC national programme · CROSS — Civil state funding for neutral-atom fault tolerance in Europe. [source]