Quantum paper

Quantum error correction (logical qubits below threshold)

Crossed theoretical threshold for scalable quantum computing; demonstrated exponential error suppression on real hardware for the first time, moving from physics milestone to engineering milestone.

What to watch next

Fault-tolerant quantum computers with 10+ logical qubits demonstrating practical speedup (2025-2026); Riverlane's MegaQuOp (1 million error-free operations) target by 2026.

Key sub-ideas & techniques

• Surface code below threshold — Google Willow (Dec 2024, 105 qubits) was the first hardware to show that increasing the surface-code distance suppresses logical error exponentially — the long-promised threshold theorem realized in silicon. [source]
• Logical qubits with virtualization — Quantinuum + Microsoft demonstrated 4 logical qubits with 800x lower error than physical qubits using ion-trap hardware and run-time mid-circuit measurement, validating a different path to QEC. [source]
• Bivariate bicycle / qLDPC codes — IBM's bivariate bicycle codes (Nature 2024) need ~10x fewer physical qubits per logical qubit than the surface code, potentially shrinking the path to fault tolerance from millions of qubits to ~hundreds of thousands. [source]
• Cat qubits & bosonic codes — Encoding a logical qubit in the photons of a microwave cavity (Alice & Bob, AWS) intrinsically suppresses bit-flip errors, reducing the QEC overhead and offering an alternative to surface codes. [source]
• Real-time decoding hardware — Riverlane's DD1 and Google's custom decoders move syndrome decoding into dedicated FPGA / ASIC, the missing piece for sustained logical operation — the 'CPU' for the quantum 'GPU'. [source]
• Logical-qubit advantage on real applications (neutral atoms) — First demonstration that logical qubits outperform physical qubits on an end-to-end real-world task (differential equations) on a neutral-atom processor at 99.4% gate fidelity across 1,000 equations. [source]
• Barbell codes (qLDPC) — A new family of quantum low-density parity-check error-correcting codes designed for IQM's superconducting Constellation processor, reducing logical error rates and physical-qubit overhead versus the surface code. [source]

Current frontier

• Google Willow (December 2024): 105-qubit processor achieved surface code error suppression below threshold with distance-7 code at 0.143% per-cycle logical error rate; first demonstration of exponential error suppression with increasing code size [source]
• Microsoft-Quantinuum (April 2024): Demonstrated 4 logical qubits with error rates 800x lower than physical qubits; 14,000+ experiments without error using trapped-ion hardware with qubit virtualization [source]
• IBM (2024): Surface code distance-5 implementation with logical error suppression, decoding in 135 microseconds on laptop; bivariate bicycle codes show 27x speedup at 0.3% circuit-level error rates [source]
• Quantinuum Helios (2025): 3rd generation ion-trap quantum computer with 99.921% 2-qubit gate fidelity; first complete quantum chemistry simulation using QEC on real hardware [source]
• Riverlane DD1 QEC Chip (2024): Dedicated quantum error correction ASIC/FPGA achieving logical error rate of 1 in a trillion; published in Nature Electronics with end-to-end hardware validation [source]
• NVIDIA Ising open AI models accelerate QEC decoding/calibration with sub-microsecond latency, 2.5x speedup and 3x accuracy gains over classical baselines. [source]
• US federal industrial policy is now explicitly steering quantum hardware build-out at the foundry level — a structural shift from research grants to manufacturing capacity formation, with $2B in CHIPS funding distributed across nine vendors on May 21, 2026. [source]
• Flatiron Institute CCQ + Boston University demonstrated (Science, May 21 2026) that a tensor-network algorithm, running on a laptop, can classically simulate the same 100-qubit highly-entangled dynamics problem D-Wave used to claim 'beyond-classical' computation with its 5,000-qubit Advantage2 annealer in March 2025 — resetting where the quantum-advantage line sits. [source]
• IBM disclosed $10B five-year quantum push (May 28, 2026) spanning R&D, manufacturing, partnerships and the Anderon foundry with DoC ($1B CHIPS proposed); targets Starling fault-tolerant machine by 2029. [source]
• On a trapped-ion QCCD processor, two optimized QEC code constructions (12-qubit Knill-inspired and 16-qubit tesseract colour code) combined with scalable error detection achieve logical error rates 11x to 800x lower than physical-circuit baselines; now published in Nature (vol 654, pp 349-355, 2026). [source]

Key people

• Hartmut Neven Founder and Lead, Google Quantum AI; VP Engineering · Google [source]
• John Preskill Director, Institute for Quantum Information & Matter; Professor of Theoretical Physics · California Institute of Technology (Caltech) [source]
• Ilyas Khan Founder & Chief Product Officer; Vice-Chairman of Board · Quantinuum [source]
• Barbara Terhal Professor of Quantum Information; Research Scientist · QuTech & DIAM, Delft University of Technology (TU Delft) [source]
• Steve Brierley Founder and CEO · Riverlane [source]
• David Hayes Senior Quantum Physicist; Logical Qubit Research Lead · Quantinuum [source]

Startups & labs to watch

• PsiQuantum PsiQuantum (photonic quantum computing) · STARTUP · Significant DARPA backing; private funding round details proprietary — DARPA US2QC program finalist (Feb 2025) pursuing surface codes on photonic qubits; broke ground on largest US quantum computing project at Illinois facility; targeting utility-scale quantum computer by 2033 [source]
• Atom Computing Atom Computing (neutral-atom quantum computing) · STARTUP · Series B/C rounds; corporate backing from aerospace partners — Scaling neutral-atom systems for QEC; announced 1,000+ qubit demonstration targets; competing with Quantinuum (trapped ions) and Google (superconducting) on QEC roadmaps [source]
• Alice & Bob Alice & Bob (bosonic quantum computing) · STARTUP · $50M+ Series B; European backing — Developing cat-qubits and bosonic codes as alternative to surface codes; co-hosted Fault Tolerance Summit (Les Houches 2024); raised $50M+ Series B [source]
• Anderon IBM (spinout) + U.S. Department of Commerce · STARTUP · $2B total ($1B IBM cash + IP/assets; $1B proposed CHIPS Act incentive) — First purpose-built US quantum foundry — provides shared, scaled 300mm fabrication for IBM, Quantinuum, Diraq, Microsoft and other modalities, addressing the wafer-supply bottleneck for fault-tolerant systems. [source]